nvmexplorer_src.input_defs package¶
Submodules¶
nvmexplorer_src.input_defs.access_pattern module¶
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class
nvmexplorer_src.input_defs.access_pattern.PatternConfig(exp_name='default', benchmark_name='test', read_freq=- 1, total_reads=- 1, read_size=8, write_freq=- 1, total_writes=- 1, write_size=8, workingset=1, total_ins=- 1)¶ Bases:
object
nvmexplorer_src.input_defs.cell_cfgs module¶
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class
nvmexplorer_src.input_defs.cell_cfgs.FeFETCellConfig(cell_file_path='../../data/cell_cfgs/FeFET.cell', access_CMOS_width=0.01, access_Vdrop=0.01, cell_area_F2=15, r_on_set_v=30000.0, r_off_set_v=30000.0, r_on_reset_v=20000000000.0, r_off_reset_v=20000000000.0, r_on_read_v=70000.0, r_off_read_v=20000000000.0, r_on_half_reset=23000000000.0, cap_on='1e-16', cap_off='1e-16', read_mode='current', read_voltage=- 0.03, read_power=0.0014, reset_mode='voltage', reset_voltage=- 2.0, reset_pulse=20, reset_energy=0.0002, set_mode='voltage', set_voltage=2.0, set_pulse=20, set_energy=0.0029, mlc=1, read_floating=False, mem_cfg_base='\n-DesignTarget: RAM\n-DeviceRoadmap: LSTP\n-LocalWireType: LocalAggressive\n-LocalWireRepeaterType: RepeatedNone\n-LocalWireUseLowSwing: No\n-GlobalWireType: GlobalAggressive\n-GlobalWireRepeaterType: RepeatedNone\n-GlobalWireUseLowSwing: No\n-Routing: H-tree\n-InternalSensing: true\n-Temperature (K): 350\n-BufferDesignOptimization: balanced\n')¶ Bases:
nvmexplorer_src.input_defs.cell_cfgs.NVSimCellConfig-
append_cell_file()¶
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class
nvmexplorer_src.input_defs.cell_cfgs.NVSimCellConfig(cell_file_path='data/cell_cfgs/SRAM.cell', mem_cell_type='SRAM', cell_area=146, cell_ratio=1.46, access_type='CMOS')¶ Bases:
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generate_cell_file()¶
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class
nvmexplorer_src.input_defs.cell_cfgs.PCMCellConfig(cell_file_path='../../data/cell_cfgs/PCM.cell', access_CMOS_width=6, cell_area_F2=19, r_on=1000, r_off=1000000, read_mode='voltage', read_current=40, read_voltage=1, read_energy=2, reset_mode='current', reset_current=10, reset_pulse=40, set_mode='current', set_current=0.2, set_pulse=150, mlc=1, mem_cfg_base='\n-DesignTarget: RAM\n-DeviceRoadmap: LOP\n-LocalWireType: LocalAggressive\n-LocalWireRepeaterType: RepeatedNone\n-LocalWireUseLowSwing: No\n-GlobalWireType: GlobalAggressive\n-GlobalWireRepeaterType: RepeatedNone\n-GlobalWireUseLowSwing: No\n-Routing: H-tree\n-InternalSensing: true\n-Temperature (K): 350\n-BufferDesignOptimization: balanced\n')¶ Bases:
nvmexplorer_src.input_defs.cell_cfgs.NVSimCellConfig-
append_cell_file()¶
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class
nvmexplorer_src.input_defs.cell_cfgs.RRAMCellConfig(cell_file_path='../../data/cell_cfgs/RRAM.cell', access_CMOS_width=6, cell_area_F2=53, r_on_set_v=100000, r_off_set_v=10000000, r_on_reset_v=100000, r_off_reset_v=10000000, r_on_read_v=1000000, r_off_read_v=10000000, r_on_half_reset=500000, cap_on='1e-16', cap_off='1e-16', read_mode='current', read_voltage=0.4, read_power=0.16, reset_mode='voltage', reset_voltage=2.0, reset_pulse=10, reset_energy=0.6, set_mode='voltage', set_voltage=2.0, set_pulse=10, set_energy=0.6, mlc=1, read_floating=False, mem_cfg_base='\n-DesignTarget: RAM\n-DeviceRoadmap: LOP\n-LocalWireType: LocalAggressive\n-LocalWireRepeaterType: RepeatedNone\n-LocalWireUseLowSwing: No\n-GlobalWireType: GlobalAggressive\n-GlobalWireRepeaterType: RepeatedNone\n-GlobalWireUseLowSwing: No\n-Routing: H-tree\n-InternalSensing: true\n-Temperature (K): 350\n-BufferDesignOptimization: balanced\n')¶ Bases:
nvmexplorer_src.input_defs.cell_cfgs.NVSimCellConfig-
append_cell_file()¶
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class
nvmexplorer_src.input_defs.cell_cfgs.SRAMCellConfig(cell_file_path='../../data/cell_cfgs/SRAM.cell', access_CMOS_width=1.31, nmos_width=2.08, pmos_width=1.23, cell_area_F2=0.0, read_mode='voltage', mem_cfg_base='\n-DesignTarget: RAM\n-DeviceRoadmap: LOP\n-LocalWireType: LocalAggressive\n-LocalWireRepeaterType: RepeatedNone\n-LocalWireUseLowSwing: No\n-GlobalWireType: GlobalAggressive\n-GlobalWireRepeaterType: RepeatedNone\n-GlobalWireUseLowSwing: No\n-Routing: non-H-tree\n-InternalSensing: false\n-Temperature (K): 350\n-BufferDesignOptimization: balanced\n')¶ Bases:
nvmexplorer_src.input_defs.cell_cfgs.NVSimCellConfig-
append_cell_file()¶ Appends necessary parameters to NVSim cell file to prepare for simulation
- Parameters
startHnd (int, optional) – Start index, defaults to 1
endHnd (int, optional) – End index, defaults to 0xFFFF
uuids (list, optional) – a list of UUID strings, defaults to None
- Returns
List of returned
bluepy.btle.Characteristicobjects- Return type
list
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class
nvmexplorer_src.input_defs.cell_cfgs.STTRAMCellConfig(cell_file_path='../../data/cell_cfgs/STTRAM.cell', access_CMOS_width=6, cell_area_F2=54, r_on=3000, r_off=6000, read_mode='current', read_voltage=0.25, min_sense_voltage=25, read_power=30, reset_mode='current', reset_current=80, reset_pulse=10, reset_energy=1, set_mode='current', set_current=80, set_pulse=10, set_energy=1, mlc=1, read_floating=False, mem_cfg_base='\n-DesignTarget: RAM\n-DeviceRoadmap: LOP\n-LocalWireType: LocalAggressive\n-LocalWireRepeaterType: RepeatedNone\n-LocalWireUseLowSwing: No\n-GlobalWireType: GlobalAggressive\n-GlobalWireRepeaterType: RepeatedNone\n-GlobalWireUseLowSwing: No\n-Routing: H-tree\n-InternalSensing: true\n-Temperature (K): 350\n-BufferDesignOptimization: balanced\n')¶ Bases:
nvmexplorer_src.input_defs.cell_cfgs.NVSimCellConfig-
append_cell_file()¶
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nvmexplorer_src.input_defs.nvsim_interface module¶
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class
nvmexplorer_src.input_defs.nvsim_interface.NVSimInputConfig(mem_cfg_file_path='../../data/mem_cfgs/test_SRAM.cfg', process_node=45, opt_target='ReadLatency', word_width=64, capacity=4, cell_type=<nvmexplorer_src.input_defs.cell_cfgs.SRAMCellConfig object>)¶ Bases:
object-
generate_mem_cfg()¶ Creates a memory config file using characteristics of
NVSimInputConfigobject to be used as an input to NVSim
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class
nvmexplorer_src.input_defs.nvsim_interface.NVSimOutputConfig(exp_name='default', input_cfg=<nvmexplorer_src.input_defs.nvsim_interface.NVSimInputConfig object>, read_latency=-1, read_bw=-1, read_energy=-1, write_latency=-1, write_bw=-1, write_energy=-1, leakage_power=-1, area=-1, area_efficiency=-1)¶ Bases:
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print_summary()¶ Prints a summary of the parsed NVSim output results
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nvmexplorer_src.input_defs.nvsim_interface.parse_nvsim_output(filepath='output_examples/sram_0', input_cfg=<nvmexplorer_src.input_defs.nvsim_interface.NVSimInputConfig object>)¶ Returns a
NVSimOutputConfigobject which gets populated with the output results in parsed from file_path.- Parameters
filepath (String) – path to NVSim output file
input_cfg (
NVSimInputConfigobject) –NVSimIntputConfigobject that was used to create the NVSim output
- Returns
NVSimOutputConfigobject containing parsed NVSim results- Return type