WEBVTT 00:01.000 --> 00:04.000 - Hi my name is Lillian Pentecost, and today I'm sharing NVMExplorer. 00:05.000 --> 00:09.000 - There's an actively expanding field of emerging and embeddable non-volatile memory technologies 00:10.000 --> 00:14.000 - that can enable denser more energy-efficient future on-chip memory. 00:15.000 --> 00:18.000 - However, each of these proposals is in different stages of development 00:19.000 --> 00:25.000 - and offer different fundamental trade-offs in terms of density, read, write, and reliability characteristics. 00:26.000 --> 00:30.000 - So, as an architect or system designer, I might ask 00:30.000 --> 00:34.000 - which of these technologies are most promising for my system and why. 00:35.000 --> 00:41.000 - And, as an application expert, I might ask which proposals are best suited for the demands of my workload. 00:42.000 --> 00:47.000 - As a device designer, I might ask where should I be pushing innovation, 00:48.000 --> 00:53.000 - where do I stack up against other proposals, and which characteristics are limiting adoption of this cell design? 00:54.000 --> 01:00.000 - NVMExplorer is a cross-stack design exploration framework to guide each of these types of questions. 01:01.000 --> 01:06.000 - Our framework enables investigation, comparison, and evaluation of emerging eNVMs 01:07.000 --> 01:10.000 - with application characteristics and system constraints in-the-loop. 01:11.000 --> 01:15.000 - Here, I'm showing NVMExplorer's interactive web-based visualization tool 01:16.000 --> 01:22.000 - with an example study across published eNVM proposals from 2018 to 2020 01:23.000 --> 01:29.000 - and using spec2017 memory traffic patterns to give a sense of some of the framework's capabilities. 01:30.000 --> 01:38.000 - For each technology, we identify what are the most optimistic (in green) and pessimistic (in red) cell level characteristics. 01:39.000 --> 01:45.000 - In this view, I'm showing STTRAM (the plus signs) and PCM (the x's) 01:46.000 --> 01:52.000 - against two comparison points derived from industry publications-- RRAM in yellow and SRAM in blue. 01:53.000 --> 01:58.000 - Focusing on these bottom three plots, we see compelling read characteristics for each eNVM 01:59.000 --> 02:09.000 - even under pessimistic cell assumptions, though the expected write latency and energy varies widely among STT, RRAM and PCM. 02:10.000 --> 02:14.000 - As indicated on the data filter and systems constraint selections on the right, 02:15.000 --> 02:17.000 - we're looking at a ton of data right now. 02:18.000 --> 02:21.000 - Let's filter to answer a more specific question-- 02:22.000 --> 02:25.000 - which technology could replace my 16MB LLC? 02:26.000 --> 02:31.000 - To guide this question, we'll filter to 16MB iso-capacity across technologies, 02:32.000 --> 02:36.000 - and we might already notice STT has pareto-optimal read characteristics, 02:37.000 --> 02:42.000 - though RRAM offers competitive read, write, and density compared to SRAM -- 02:43.000 --> 02:46.000 - especially in contrast to pessimistic definitions. 02:47.000 --> 02:53.000 - However, array-level characteristics in isolation are not enough to sell us on a particular technology-- 02:54.000 --> 02:57.000 - how are these memory arrays going to be used by the target system? 02:58.000 --> 03:03.000 - Thus, we also provide application-aware results, which we see in these top three plots: 03:04.000 --> 03:09.000 - Total operating power, so, leakage plus dynamic, under different workload access patterns 03:10.000 --> 03:17.000 - plotted against the number of read accesses per second reveals that all of the eNVMs offer lower power solutions than SRAM, 03:18.000 --> 03:20.000 - with PCM as a clear winner across many workloads, 03:21.000 --> 03:26.000 - where each column of data points here corresponds to a particular workload's traffic balance; 03:27.000 --> 03:35.000 - Total access latency versus number of write accesses per second shows that STT and RRAM are offering improved performance 03:36.000 --> 03:38.000 - compared to SRAM even under high write pressure; 03:39.000 --> 03:45.000 - However, we see in the projected memory lifetime that RRAM endurance is an open research question and, 03:46.000 --> 03:52.000 - as such, STT and PCM are better suited for further optimization and iterative exploration 03:53.000 --> 03:58.000 - using NVMExplorer to refine NVM characteristics and system constraints. 03:59.000 --> 04:02.000 - Through just this brief tour and a limited set of design points, 04:03.000 --> 04:09.000 - I hope you can see a glimpse of both the promise and the caveats of comparing and evaluating future on-chip memory. 04:10.000 --> 04:14.000 - If you saw anything you'd like to explore yourself, you can interact with this beta version at [Interactive Mode] 04:15.000 --> 04:16.000 - Thank you!