- Hi my name is Lillian Pentecost, and today I'm sharing NVMExplorer.
- There's an actively expanding field of emerging and embeddable non-volatile memory technologies
- that can enable denser more energy-efficient future on-chip memory.
- However, each of these proposals is in different stages of development
- and offer different fundamental trade-offs in terms of density, read, write, and reliability characteristics.
- So, as an architect or system designer, I might ask
- which of these technologies are most promising for my system and why.
- And, as an application expert, I might ask which proposals are best suited for the demands of my workload.
- As a device designer, I might ask where should I be pushing innovation,
- where do I stack up against other proposals, and which characteristics are limiting adoption of this cell design?
- NVMExplorer is a cross-stack design exploration framework to guide each of these types of questions.
- Our framework enables investigation, comparison, and evaluation of emerging eNVMs
- with application characteristics and system constraints in-the-loop.
- Here, I'm showing NVMExplorer's interactive web-based visualization tool
- with an example study across published eNVM proposals from 2018 to 2020
- and using spec2017 memory traffic patterns to give a sense of some of the framework's capabilities.
- For each technology, we identify what are the most optimistic (in green) and pessimistic (in red) cell level characteristics.
- In this view, I'm showing STTRAM (the plus signs) and PCM (the x's)
- against two comparison points derived from industry publications-- RRAM in yellow and SRAM in blue.
- Focusing on these bottom three plots, we see compelling read characteristics for each eNVM
- even under pessimistic cell assumptions, though the expected write latency and energy varies widely among STT, RRAM and PCM.
- As indicated on the data filter and systems constraint selections on the right,
- we're looking at a ton of data right now.
- Let's filter to answer a more specific question--
- which technology could replace my 16MB LLC?
- To guide this question, we'll filter to 16MB iso-capacity across technologies,
- and we might already notice STT has pareto-optimal read characteristics,
- though RRAM offers competitive read, write, and density compared to SRAM --
- especially in contrast to pessimistic definitions.
- However, array-level characteristics in isolation are not enough to sell us on a particular technology--
- how are these memory arrays going to be used by the target system?
- Thus, we also provide application-aware results, which we see in these top three plots:
- Total operating power, so, leakage plus dynamic, under different workload access patterns
- plotted against the number of read accesses per second reveals that all of the eNVMs offer lower power solutions than SRAM,
- with PCM as a clear winner across many workloads,
- where each column of data points here corresponds to a particular workload's traffic balance;
- Total access latency versus number of write accesses per second shows that STT and RRAM are offering improved performance
- compared to SRAM even under high write pressure;
- However, we see in the projected memory lifetime that RRAM endurance is an open research question and,
- as such, STT and PCM are better suited for further optimization and iterative exploration
- using NVMExplorer to refine NVM characteristics and system constraints.
- Through just this brief tour and a limited set of design points,
- I hope you can see a glimpse of both the promise and the caveats of comparing and evaluating future on-chip memory.
- If you saw anything you'd like to explore yourself, you can interact with this beta version at [Interactive Mode]
- Thank you!